OTIR
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COMPUTE

UNBOUND

01 // THE FRAGMENTATION

The silicon landscape has fractured. The pursuit of performance has created a babel of proprietary languages, locked ecosystems, and isolated architectures. Optimization for one is obsolescence for another. This is a tax on human progress.

WE REJECT THE NOTION THAT HARDWARE SPECIFICITY REQUIRES SOFTWARE ISOLATION. WE PROPOSE A UNIFIED INTERMEDIATE REPRESENTATION BASED ON THE ONLY CONSTANT IN MODERN COMPUTE: THE TILE.
READ THE SPECIFICATION

SUPPORTED_ARCHITECTURES

[ TARGET LIST ]

OTIR provides a unified lowering path for the world's most capable silicon. From massive datacenter GPUs to specialized edge NPUs, the abstraction remains constant.

THE_SYNTAX

[ IR_PREVIEW ]

OTIR code describes intent, not implementation. It defines explicit memory hierarchies (`Global`, `Workgroup`, `Private`) and asynchronous data movement, allowing the compiler to perform architectural-specific optimizations such as pipeline software prefetching and warp scheduling.


> NO THREADS
> NO WARPS
> JUST DATA FLOW
matmul_f16.mlir SIZE: 12KB 
// OTIR: Explicit Tiled Architecture
func @matmul_kernel(
    %A: !otir.tile<128x128, f16, #Global>, 
    %B: !otir.tile<128x128, f16, #Global>
) {
    // Alloc L1/Shared Memory Buffer
    %buf = otir.alloc() : !otir.tile<128x128, f16, #Workgroup>

    // Initiate Async DMA Transfer
    %token = otir.dma_copy_async %A -> %buf

    // ... Compute / Overlap ...

    // Synchronization Barrier
    otir.wait %token

    // Matrix Multiply on Tensor Core / Cube Unit
    %res = otir.matmul %buf, %regs
}